Guest Editorial Special Section on System-on-Chip Integration: Challenges and Implications

SYSTEM-ON-CHIP (SOC) is the term used for a fully integrated circuit (IC), where few if any additional electronic components are required to make a complete system. The term has had many and varied definitions over time. Today, a typical SOC IC can be anything from a complex mixed-signal product, where a wide range of functionality such as RF, analog, power management, and digital coexist on-chip, to a complex digitalonly product. It can contain high current and/or high voltage outputs and precision operational amplifiers and detectors. It is thus apparent that virtually every IC development can be incorporated under the SOC umbrella. The IEEE Systemon-Chip Conference (IEEE-SOCC), currently in its 26th year, covers the majority of areas of possible integration in its technical program. This Special Section is partially based on a selection of papers submitted to the 2006 IEEE-SOCC, which have been extended and revised. Due to the intense interest in the subjects of this Special Section, additional submissions not connected to the IEEE-SOCC have also been included. A total of 38 high-quality submissions have been considered for this Special Section. Reducing this Special Section down to these nine included papers has been a difficult task. The guest editors would like to acknowledge the 2006 IEEE-SOCC Track Chairs and the Technical Program Chair Dr. Thanh Tran. We are also highly indebted to the IEEE-TVLSI reviewers and the Editorial Board, for the success of this Special Section. Contributions ranging from emerging research in the SOC area to designs that advance specific aspects of SOC implementation, all the way to complete circuit design, are included in these nine papers. Interconnect aspects are addressed in the first two papers, “Utilizing Redundancy for Timing Critical Interconnect,” by Hu et al. and “3-D Topologies for Networks-on-Chip,” by Pavlidis and Friedman. Timing performance and tolerance to open faults and variations is the focus of the first paper. In the second paper, topologies that develop from merging networks-on-chip (NoCs) with 3-D circuits are explored and innovative 3-D topologies proposed. Latency and power models describing these topologies are developed and used in an assessment of optimal power consumption and speed. In “Applying CDMA Technique to Network-on-Chip,” Wang et al. focus on achieving data-transfer concurrency eliminating data transfer latency variances caused by packet routing in a point-to-point NoC. The focus of “An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration,” by Noguchi et al. is on an on-chip multichannel waveform monitor in terms of